##-----------------------------------------------------------------------------
## Title         : FPGA, Syncplicity Pro Batch Script
## Project       : Generic
##-----------------------------------------------------------------------------
## File          : AsicTestSyn.tcl
## Author        : Ryan Herbst, ryan@amaroq.com
## Created       : 03/06/2008
##-----------------------------------------------------------------------------
## Description:
## Synplify Pro Batch script for syntesizing the ASIC Test FPGA.
## This script is passed to the synplify_pro program in order synthesize the
## FPGA.
##-----------------------------------------------------------------------------
## Copyright (c) 2007 by Ryan Herbst. All rights reserved.
##-----------------------------------------------------------------------------
## Modification history:
## 03/06/2008: created.
##-----------------------------------------------------------------------------

## Set Project
project -new

## Compile In Syn Directory
impl -add "syn"

## Extract source directory from environment
set pgpsrc  $::env(PGPSRC);
set pgpappl $::env(PGPAPPL);
set rtlsrc  $::env(RTLSRC);
set sdcfile $::env(SDCFILE);

## Set Part, Packet & Speed
set_option -technology VIRTEX4
set_option -part XC4VFX20
set_option -package FF672
set_option -speed_grade -10

## Version Data
add_file $rtlsrc/Version.vhd

## PGP Source Files
add_file $pgpsrc/PgpVersion.vhd
add_file $pgpsrc/PgpAckRx.vhd
add_file $pgpsrc/PgpCellRx.vhd
add_file $pgpsrc/PgpCellTx.vhd
add_file $pgpsrc/PgpMgtWrap.vhd
add_file $pgpsrc/PgpPhy.vhd
add_file $pgpsrc/PgpRxTrack.vhd
add_file $pgpsrc/PgpTxSched.vhd
add_file $pgpsrc/PgpTop.vhd
add_file $pgpappl/PgpClkGen.vhd
add_file $pgpappl/PgpCmdSlave.vhd
add_file $pgpappl/PgpRegSlave.vhd
add_file $pgpappl/PgpPicRemBuff.vhd

## RTL Source Files
add_file $rtlsrc/DisplayCharacters.vhd
add_file $rtlsrc/DisplayControl.vhd
add_file $rtlsrc/AcqControl.vhd
add_file $rtlsrc/AdcReadout.vhd
add_file $rtlsrc/PgpDataBuffer.vhd
add_file $rtlsrc/PgpFrontEnd.vhd
add_file $rtlsrc/PotShift.vhd
add_file $rtlsrc/RegControl.vhd
add_file $rtlsrc/SelRowCol.vhd
add_file $rtlsrc/SetGain.vhd
add_file $rtlsrc/AsicTestCore.vhd
add_file $rtlsrc/AsicTest.vhd

## Additional map options
set_option -frequency 20
set_option -disable_io_insertion 1

## Additional placeAndRoute options
set_option -write_apr_constraint 0

##--Set result format/file last
project -result_file AsicTest.edn
project -log_file    AsicTest.srr

##-- Constraint file
add_file -constraint $sdcfile

## Compile The Project
project -run