Perl Script For Xilinx/Synplicity Builds
Note: I no longer use these scripts. I have converted to a Makefile setup for FPGA builds.
This perl script is used to build a Xilinx FPGA from the command line, using Synplify PRO as a synthesis tool. I wrote this script to avoid using the Xilinx ISE project navigator when building my FPGAs. This script is called in the following fashion:
buildFpga.pl proj_top_dir output_dir [syn tran map par time bit prom sim]
proj_top_dir identifies the top level project directory. All paths set in the config section of the script use this directory as a base. The output_dir is where the synthesis files and output files will be located. If no other args are passed a default set of actions will be executed. Otherwise the the actions that should be performed by the script will be passed on the command lines. The supported actions are:
- syn- Synthesize the project with synplify_pro (selected by default)
- tran – Perform the translation step in Xilinx ISE (selected by default)
- map – Perform the map step in Xilinx ISE (selected by default)
- par – Perform the place & route step in Xilinx ISE (selected by default)
- time – Perform the timing report generation step in Xilinx ISE (selected by default)
- bit – Perform the bit file generation step in Xilinx ISE (selected by default)
- prom – Perform the prom file generation step in Xilinx ISE (selected by default)
The first section of this script contains variable settings that server as configuration options. These variables should be set by the user to customize the script to their design.
AsicTestSyn.tcl
This script is used by Synplicity in the synthesis step of the FPGA build. This script is identified in the buildFpga script above. This script file defines the VHDL/Verilog source files used during synthesis. It also contains some configuration settings used during the synthesis step of the build process.
