Ryan Herbst

This page contains scripts that I have written for use with Mentor Graphics, Viewdraw. Viewdraw is a schematic capture program used to create netlists for PCB boards.

excelList.pl

This script will convert the partlist ASCII file output by Viewdraw’s part lister into an Excel formatted bill of materials. This script can be run from the command line or from within Viewdraw itself. This perl script uses OLE extensions to directly input data into the Excel file and format the data for readability. The script works regardless of the format of the Viewdraw partlist file. The script will automatically detect the name and width of the Viewdraw partlist columns.

1. In order to add this script to the command menu open DxDesigner and to the following:
2. Select the tools->customize menu item.
3. Enter “Excel Part List” In the “Menu Text” field.
4. Enter “C:\Perl\bin\perl.exe” in the “Command” field (or the path to your perl software)
5. Enter “path_to_script\excelList.pl $BLOCKNAME $PROJDIR” in the “Arguments” field.
6. Enter “$PROJDIR” in the “Initial Directory” field.
7. Click the “Add” button.

Now that the ExcelList script is setup you should now customize your partlist.ini file for you specific needs. The output file from the partlister should be $BLOCKNAME.lst. The ExcelList script will read this file and generate the Excel BOM file. The newly created file will be automatically saved as $BLOCKNAME_bom.xls.

pads2Ucf.pl

This script allows you to generate a Xilinx UCF file containing signal pin locations extracted from a PADS netlist. This script is called with three arguments. The first is the input pads file, the second is the reference designator of the Xilinx FPGA in the netlist, the third is the name of the output UCF file to generate.

This script will format the net names to by converting names such as:

ADC_CLK

in the schematic to

adcClk

in the UCF file. Bussed signals with a name such as

ADC_DATA10

will be converted to

adcData(10)

A location and IOSTANDARD attribute will be generated for each pin on the FPGA.