Makefile For Xilinx/Synplicity Builds
The following Makefile and tcl script are used to build FPGA projects.
This file is the top level makefile for the entire build process. In order to make this as portable as possible I keep the number of command line options to a minimum. All of the synplicity options are contained in the .tcl batch script (included below). All of the Xilinx options are contained in options files that are read in by the various Xilinx programs during the synthesis process. I have included examples below. Pleas note that the Makefile does not check dependencies. Typing make will force a rebuild from scratch of your project.
The makefile assumes the following subdirectories exist under the top level project directory:
- rtl – Source code for FPGA
- syn – Directory containing the build files included on this page
- xil_cores – Directory containing cores generate by coregen
- images – Directory to place the resulting prom file
The rtl subdirectory should also include the following files:
- ProjectVersion.vhd – A File contaning a version constant that is used in the design. This field is included in the name of the generated image.
- Project.ucf – Xilinx constraints file
- Project.sdc – Synplicity constraints file
The version line in the ProjectVersion.vhd files should look like:
constant FpgaVersion : std_logic_vector(31 downto 0) := x”BAFB0002″; — MAKE_VERSION
The ucf file should contain information about the target device such as:
CONFIG PART = xc4vfx20-ff672-11;
The .rcl file is read in by synplicity when it is called from the top level makefile. A number of environment variables are passed in order to allow synplicity to find the full patch to all of the source files while keeping the Makefile portable.
The following files are the various options files that are read in by xilinx during placement, routing and the other Xilinx processes.
