Ryan Herbst

Professional Experience

May 2004 to Present

SLAC National Accelerator Laboratory
Menlo Park, Ca
Sr. Electrical Engineer

July 2001 to May 2004

Candera Inc.
Milpitas, Ca
Member of Technical Staff

Designed IO sub-system of main system board. This included the main PCI bus, PCI Bus arbiter (Altera CPLD), PCMCIA controller and card interface, system interrupt router and general glue logic (Altera CPLD). I also played key role in the bring up and debug of this board, assisting software engineers in the initial driver and BSP debug.

Researched and architected virtualized Cache design. I worked closely with system software engineers in the definition of the design requirements and the command/data flows. I designed and documented the methods used to store and locate cached data as well as the high level architecture of the cache logic.

Designed, implemented and tested Fibre Channel elastic buffer circuit in a Xilinx FPGA.

Designed cost reduced PMC processor card to replace costly off the shelf processor card. This card was eventually integrated into the main system board to further reduce cost.

Worked closely with NP software engineers to identify areas of the code that were costing NP CPU cycles due to multiple external memory accesses. I used the findings to architect, document and implement an offload processing FPGA implemented in a Xilinx XCV2000 interfacing to a network processor over a 133Mhz LVCMOS interface. The FPGA consisted of two DDR SRAM interfaces both operating at 133Mhz.

Served as the technical lead for the hardware development of Candera’s next generation architecture. My duties on this project included the documentation of the overall hardware architecture and the individual functional blocks existing in the system. This work included a detailed analysis of the traffic flow through the system, identifying the congestion points and detailing solutions for congestion management. My duties also included the scheduling of the hardware implementation from functional specifications through the system implementation and testing. This included working with the other team leads to link cross functional dependencies as well as scheduling parts of the design that were implemented by outside vendors. I was responsible for the technical oversight of the overall implementation including schematic design, PCB layout and mechanical design.

My direct responsibilities of this project included the oversight of a SPI4.2 to SPI4.3 bridge design implemented in a Xilinx Vitex2 FPGA. Although I authored the functional specification and requirements an outside vendor performed the actual implementation. I personally architected, designed and implemented a SPI4.2 based traffic controller which interfaced our network processor to a SPI4.2 backplane switch. This device also interfaced to a general-purpose processor through a high speed FIFO interface. The main intelligence of this device consisted of a frame lookup engine that would process, modify and route initial Fibre channel command frames as they were received from various hosts. This FPGA also handled the congestion management function in the system.

Relevant Skills:

• Direct experience with Verilog, Xilinx ISE and Modelsim PE
• Experience with Modelsim PE including Verilog PLI & TCP/IP based verification
• Familiar with Fibre Channel and SCSI protocols
• Familiar with SPI4.2
• Familiar with Hyper-transport and Rapid-IO
• Solid skills in Verilog FPGA design and implementation
• C coding and software debug
• Perl scripting
• Solid lab bring up and debug skills
• Viewdraw schematic entry

August 1998 to July 2001

Mayan Networks
San Jose, Ca
Senior Hardware Engineer, Technical Lead

Technical lead for a team of engineers developing telecom and data processing network equipment.

At MAYAN I played a key role in a small team in the design of a 19 card CPCI based chassis product. This included back plane design, support of mechanical engineers and common card interfaces. I also assisted in the early software development of the PCI address mapping and bridge configuration.

I designed the central timing card for the Mayan Unifier. This card functions as a system timing source, a CPCI bridge and arbitration card and a platform for attaching an OC3 ring interface daughter card. The timing logic uses a Connor Winfield timing module with a custom state machine implemented in a Xilinx CPLD. This state machine automatically selects between the multiple timing sources available to the system.

I designed redundant CPCI arbitration and clock source logic used on the timing and management cards in the Unifier. This circuit contains a custom arbiter implemented in a Xilinx CPLD. This logic allows the redundant PCI system cards to support switching of the arbitration and clocking while traffic is running.

I designed T1 interface card for Unifier. This card interfaces 14 electrical T1s to the Unifier SONET back plane.

I assisted in the design of system management card. This card contains the same PCI interface logic as the central timing card mentioned above.

I designed an HDLC processing card that passes data between 84DS1s on the STS12 back plane and 4 100-FX Ethernet ports. This card contains a DS0 cross connect and an MMC 3400 network processor for layer 3 IP processing.

As one of the lead hardware engineers I was involved in system level design discussions while acting as the point contact for system level hardware issues. I was also involved in the architecture design for future projects. The system level design and debug work I am involved in requires me to be familiar with the following:

• SONET/SDH frame formats, ring and linear optical interfaces
• T1/E1 & DS3 interface design and frame formats
• VHDL coding in CPLDs and FPGAs
• IP configurations and routing protocols
• Limited knowledge of ATM protocols

October 1997 to August 1998

Verilink
San Jose, Ca
Hardware Design Engineer

At Verilink as a junior hardware engineer I supported the design of a 4 port T1/E1 interface card. This card contained a DS0 and signaling cross connect which interfaced data and signaling to the AS2000 back plane. I designed and implemented the signaling cross connect FPGA which sits parallel to the data cross connect device. This FPGA is used to format the signaling data for the AS2000 back plane.

I adapted a two port T1 CDSU into a self-contained 1U box.

I also supported software engineers in the bringup and coding of various boards, including some low level C coding to configure parts during testing.

July 1996 to October 1997

Verilink
San Jose, Ca
Systems Test Engineer, Engineering Verification Test

At Verilink I performed card and system level design verification test of T1/E1 CSU and CDSU equipment. I worked closely with design engineers in system verification of new hardware and software. I wrote test plans for verification of new products.

I performed testing of new ISDN PRI interface cards. This included setting up and debugging ISDN PRI lines with local telephone company. I wrote 5ESS PRI switch emulation script for HP Idacom test equipment. This test script was used to stress test the ISDN card for multiple call setup and tear down.

Education

San Jose State University
San Jose, Ca
Graduated December 1997
B. S. Degree in Electrical Engineering

My senior project at San Jose State was a remote weather collection system. This system used an 80C550 processor to collect temperature, wind speed, wind direction and barometric pressure. This unit collected data over a 30-day period that could be downloaded to a Windows or Linux PC. In addition to designed and building the hardware, I designed and wrote the embedded software, the server software and the communications protocol for transferring data between the two.

Additional Data

• System administration skills with Linux, Windows 98, 95 & 2000 & XP
• C programming experience
• PHP & SQL web programming experience
• Java programming experience
• Filepro database programming experience
• Licensed HAM operator

References available on request.